View AD7767_4106833.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs AD7767
FEATURES
Oversampled successive approximation (SAR) architecture High performance ac and dc accuracy, low power 115.5 dB dynamic range, 32 kSPS (AD7767-2) 112.5 dB dynamic range, 64 kSPS (AD7767-1) 109.5 dB dynamic range, 128 kSPS (AD7767) -118 dB THD Exceptionally low power 8.5 mW, 32 kSPS (AD7767-2) 10.5 mW, 64 kSPS (AD7767-1) 15 mW, 128 kSPS (AD7767) High dc accuracy 24 bits, no missing codes (NMC) INL: 3 ppm (typical), 7.6 ppm (maximum) Low temperature drift Zero error drift: 15 nV/C Gain error drift: 0.0075% FS On-chip low-pass FIR filter Linear phase response Pass-band ripple: 0.005 dB Stop-band attenuation: 100 dB 2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options Flexible interfacing options Synchronization of multiple devices Daisy chain capability Power-down function Temperature range: -40C to +105C
GENERAL DESCRIPTION
The AD7767/AD7767-1/AD7767-2 are high performance 24-bit oversampled SAR analog-to-digital converters (ADC). The AD7767/AD7767-1/AD7767-2 combine the benefits of a large dynamic range and input bandwidth, consuming 15 mW, 10.5 mW, and 8.5 mW power, respectively, all contained in a 16-lead TSSOP package. Ideal for ultralow power data acquisition (such as PCI- and USB-based systems), the AD7767/AD7767-1/AD7767-2 provide 24-bit resolution. The combination of exceptional SNR, wide dynamic range, and outstanding dc accuracy make the AD7767/AD7767-1/AD7767-2 ideally suited for measuring small signal changes over a wide dynamic range. This is particularly suitable for applications where small changes on the input are measured on larger ac or dc signals. In such an application, the AD7767/AD7767-1/AD7767-2 accurately gather both ac and dc information. The AD7767/AD7767-1/AD7767-2 include an on-board digital filter (complete with linear phase response) that acts to eliminate out-of-band noise by filtering the oversampled input voltage. The oversampled architecture also reduces front-end antialias requirements. Other features of the AD7767 include a SYNC/PD (synchronization/power-down) pin, allowing the synchronization of multiple AD7767 devices. The addition of an SDI pin provides the option of daisy chaining multiple AD7767 devices. The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply using a 5 V reference. The devices operate from -40C to +105C.
APPLICATIONS
Low power PCI/USB data acquisition systems Low power wireless acquisition systems Vibration analysis Instrumentation High precision medical acquisition
RELATED DEVICES
Table 1. 24-Bit Analog-to-Digital Converters
Part No. AD7760 AD7762/ AD7763 AD7764
SYNC/PD
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND MCLK VREF+ VIN+ SUCCESSIVEAPPROXIMATION ADC VIN- REFGND DIGITAL FIR FILTER DVDD VDRIVE DGND
AD7765 AD7766 AD7766-1 AD7766-2
1
SCLK DRDY SDO
SDI
06859-001
AD7767/ AD7767-1/ AD7767-2
SERIAL INTERFACE AND CONTROL LOGIC
CS
Description 2.5 MSPS, 100 dB dynamic range 1 , on-board differential amp and reference buffer, parallel, variable decimation 625 kSPS, 109 dB dynamic range1, on-board differential amp and reference buffer, parallel/serial, variable decimation 312 kSPS, 109 dB dynamic range1, on-board differential amp and reference buffer, variable decimation (pin) 156 kSPS, 112 dB dynamic range1, on-board differential amp and reference buffer, variable decimation (pin) 128 kSPS, 109.5 dB1, 15 mW, 16-bit INL, serial interface 64 kSPS 112.5 dB1,10.5 mW, 16-bit INL, serial interface 32 kSPS, 115.5 dB1, 8.5 mW, 16-bit INL, serial interface
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Dynamic range at maximum output data rate.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD7767 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 AD7767/AD7767-1/AD7767-2 Transfer Function................ 15 Converter Operation.................................................................. 15 Analog Input Structure.............................................................. 16 Supply and Reference Voltages ................................................. 16 AD7767 Interface ........................................................................... 17 Initial Power-Up ......................................................................... 17 Reading Data............................................................................... 17 Power-Down, Reset, and Synchronization ............................. 17 Daisy Chaining ............................................................................... 18 Reading Data in Daisy Chain Mode ........................................ 18 Choosing the SCLK Frequency ................................................ 18 Daisy Chain Mode Configuration and Timing Diagrams.... 19 Driving the AD7767....................................................................... 20 Differential Signal Source ......................................................... 20 Single-Ended Signal Source ...................................................... 20 Antialiasing ................................................................................. 21 Power Dissipation....................................................................... 21 VREF+ Input Signal ....................................................................... 22 Multiplexing Analog Input Channels ...................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
8/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD7767 SPECIFICATIONS
AVDD = DVDD = 2.5 V 5%, VDRIVE = 1.8 V to 3.6 V, VREF = 5 V, MCLK = 1 MHz, common-mode input = VREF/2, TA = -40C to +105C, unless otherwise noted. Table 2.
Parameter OUTPUT DATA RATE AD7767 AD7767-1 AD7767-2 ANALOG INPUT 1 Differential Input Voltage Absolute Input Voltage Common-Mode Input Voltage Input Capacitance DYNAMIC PERFORMANCE AD7767 Dynamic Range 2 Signal-to-Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR)2 Total Harmonic Distortion (THD)2 Intermodulation Distortion (IMD)2 Test Conditions/Comments Decimate by 8 Decimate by 16 Decimate by 32 VIN+ - VIN- VIN+ VIN- Min Typ Max 128 64 32 VREF +VREF + 0.1 VREF/2 22 +VREF + 0.1 VREF/2 + 5% Unit kHz kHz kHz V p-p V V V pF
-0.1 -0.1 VREF/2 - 5%
AD7767-1 Dynamic Range2 Signal-to-Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR)2 Total Harmonic Distortion (THD)2 Intermodulation Distortion (IMD)2
AD7767-2 Dynamic Range2 Signal-to-Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR)2 Total Harmonic Distortion (THD)2 Intermodulation Distortion (IMD)2
DC ACCURACY1 Resolution Differential Nonlinearity2 Integral Nonlinearity2 Zero Error2 Gain Error2 Zero Error Drift2 Gain Error Drift2 Common-Mode Rejection Ratio2
Decimate by 8, ODR = 128 kHz Shorted inputs Full-scale input amplitude, 1 kHz tone Full-scale input amplitude, 1 kHz tone Full-scale input amplitude, 1 kHz tone Tone A = 49.7 kHz, Tone B = 53 kHz Second-order terms Third-order terms Decimate by 16, ODR = 64 kHz Shorted inputs Full-scale input amplitude, 1 kHz tone Full-scale input amplitude, 1 kHz tone Full-scale input amplitude, 1 kHz tone Tone A = 24.7 kHz, Tone B = 25.3 kHz Second-order terms Third-order terms Decimate by 32, ODR = 32 kHz Shorted inputs Full-scale input amplitude, 1 kHz tone Full-scale input amplitude, 1 kHz tone Full-scale input amplitude, 1 kHz tone Tone A = 11.7 kHz, Tone B = 12.3 kHz Second-order terms Third-order terms For all devices No missing codes Guaranteed monotonic to 24 bits 18-bit linearity
108 107
109.5 108.5 -128 -118 -133 -109
-116 -105
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Bits
111 110
112.5 111.5 -128 -118 -133 -108
-116 -105
114 112
115.5 113.5 -128 -118 -137 -108
-116 -105
24 3 20 0.0075 15 0.4 -110 7.6 0.075
50 Hz tone
ppm V % FS nV/C ppm/C dB
Rev. 0 | Page 3 of 24
AD7767
Parameter DIGITAL FILTER RESPONSE1 Group Delay Settling Time (Latency) Pass-Band Ripple Pass Band -3 dB Bandwidth Stop Band Frequency Stop-Band Attenuation REFERENCE INPUT1 VREF+ Input Voltage DIGITAL INPUTS (Logic Levels)1 VIL VIH Input Leakage Current Input Capacitance Master Clock Rate Serial Clock Rate DIGITAL OUTPUTS1 Data Format VOL VOH POWER REQUIREMENTS1 AVDD DVDD VDRIVE CURRENT SPECIFICATIONS AD7767 (Operational Current) AIDD DIDD IREF AD7767-1 (Operational Current) AIDD DIDD IREF AD7767-2 (Operational Current) AIDD DIDD IREF Static Current (MCLK Stopped) AIDD DIDD Power-Down Mode Current AIDD DIDD POWER DISSIPATION AD7767 (Operational Power) AD7767-1 (Operational Power) AD7767-2 (Operational Power)
1 2
Test Conditions/Comments
Min
Typ 37/ODR 74/ODR
Max
Unit s s dB Hz Hz Hz dB V V V A/pin pF MHz Hz
Complete settling
0.005 0.453 x ODR 0.49 x ODR 0.547 x ODR 100 +2.4 -0.3 0.7 x VDRIVE 5 1.024 1/t8 Serial 24 bits, twos complement (MSB first) ISINK = +500 A ISOURCE = -500 A 5% 5% +1.7 MCLK = 1.024 MHz 128 kHz output data rate 1.3 3.9 0.35 64 kHz output data rate 1.3 2.2 0.35 32 kHz output data rate 1.3 1.37 0.35 For all devices 0.9 1 For all devices 0.1 1 MCLK = 1.024 MHz 128 kHz output data rate 64 kHz output data rate 32 kHz output data rate 15 10.5 8.5 6 93 18 13 10.5 1 93 1.5 1.86 0.425 1.5 2.85 0.425 1.5 4.8 0.425 2 x AVDD 0.3 x VDRIVE VDRIVE + 0.3 1
0.4 VDRIVE - 0.3 +2.5 +2.5 +2.5
V V V V V
+3.6
mA mA mA mA mA mA mA mA mA mA A A A mW mW mW
Specifications for all devices, AD7767, AD7767-1, and AD7767-2. See the Terminology section.
Rev. 0 | Page 4 of 24
AD7767
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = -40C (TMIN) to +105C (TMAX), unless otherwise noted 1 Table 3.
Parameter DRDY Operation t1 t2 2 t3 t4 Limit at TMIN, TMAX 510 100 900 265 128 71 294 435 492 Unit ns typ ns min ns max ns typ ns typ ns typ ns typ ns typ ns typ ns typ Description MCLK rising edge to DRDY falling edge MCLK high pulse width MCLK low pulse width MCLK rising edge to DRDY rising edge (AD7767) MCLK rising edge to DRDY rising edge (AD7767-1) MCLK rising edge to DRDY rising edge (AD7767-2) DRDY pulse width (AD7767) DRDY pulse width (AD7767-1) DRDY pulse width (AD7767-2) DRDY low period, read data during this period
t5
tREAD 3
t DRDY - t5 n x 8 x tMCLK 0 6 60 50 25 24 10 10 10 1/t8 6 0 0 0 1 2 1 20 1 510 592 x (n + 2)
t DRDY 3 Read Operation t6 t7 t8
ns typ ns min ns max ns max ns max ns max ns max ns min ns min ns min min ns max ns min ns min ns max ns min ns max ns typ ns typ ns min ns typ tMCLK
DRDY period DRDY falling edge to CS setup time CS falling edge to SDO three-state disabled Data access time after SCLK falling edge (VDRIVE = 1.7 V) Data access time after SCLK falling edge (VDRIVE = 2.3 V) Data access time after SCLK falling edge (VDRIVE = 2.7 V) Data access time after SCLK falling edge (VDRIVE = 3.0 V) SCLK falling edge to data valid hold time (VDRIVE = 3.6 V) SCLK high pulse width SCLK low pulse width Minimum SCLK period Bus relinquish time after CS rising edge CS rising edge to DRDY rising edge DRDY falling edge to data valid setup time DRDY rising edge to data valid hold time SDI valid to SCLK falling edge setup time SCLK falling edge to SDI valid hold time SYNC/PD falling edge to MCLK rising edge MCLK rising edge to DRDY rising edge going into SYNC/PD SYNC/PD rising edge to MCLK rising edge MCLK rising edge to DRDY falling edge coming out of SYNC/PD Filter settling time after a reset or power-down
t9 t10 t11 tSCLK t12 t13 Read Operation with CS Low t14 t15 Daisy Chain Operation t16 t17 SYNC/PD Operation t18 t19 t20 t21 tSETTLING3
1 2
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V. t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum MCLK frequency is 1.024 MHz. 3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.
Rev. 0 | Page 5 of 24
AD7767
TIMING DIAGRAMS
t2
MCLK 1 8xn 1 8xn
t3 t1
DRDY
t4 t5 t5
tREAD tDRDY
06859-002
Figure 2. DRDY vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)
tDRDY
DRDY
tREAD t13
t6
CS
t10
SCLK 1 23
t7
SDO MSB
t8
t9
t11 t12
D22
D21
D20
D1
LSB
Figure 3. Serial Timing Diagram, Reading Data Using CS
CS = 0
tDRDY
DRDY
tREAD t14 t10
SCLK
1
23
24
t8
t9
t11
t15
SDO
DATA INVALID
MSB
D22
D21
D20
D1
LSB
DATA INVALID
06859-004
Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low
Rev. 0 | Page 6 of 24
06859-003
AD7767
PART OUT OF POWER-DOWN PART IN POWER-DOWN MCLK (I) A B FILTER RESET BEGINS SAMPLING C D
t18
SYNC/PD (I)
t20
t19
DRDY (O)
t21 tSETTLING
DOUT (O)
VALID DATA
INVALID DATA
VALID DATA
Figure 5. Reset, Synchronization, and Power-Down Timing Diagram
Rev. 0 | Page 7 of 24
06859-005
AD7767 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter AVDD to AGND DVDD to DGND AVDD to DVDD VREF+ to REFGND REFGND to AGND VDRIVE to DGND VIN+, VIN- to AGND Digital Inputs to DGND Digital Outputs to DGND AGND to DGND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD
1
Rating -0.3 V to +3 V -0.3 V to +3 V -0.3 V to +0.3 V -0.3 V to +7 V -0.3 V to + 0.3 V -0.3 V to +6 V -0.3 V to VREF +0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to +0.3 V 10 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
-40C to +105C -65C to +150C 150C 150.4C/W 27.6C/W 215C 220C 1 kV
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. 0 | Page 8 of 24
AD7767 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1 VREF+
2 16 15
CS SDI MCLK SCLK DRDY DGND SDO VDRIVE
06859-006
REFGND 3 VIN+ 4 VIN- 5 AGND 6 SYNC/PD 7 DVDD 8
AD7767/ AD767-1/ AD7767-2
TOP VIEW (Not to Scale)
14 13 12 11 10 9
Figure 6. 16-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 Mnemonic AVDD VREF+ Description +2.5 V Analog Power Supply. Reference Input for the AD7767. An external reference must be applied to this input pin. The VREF+ input can range from 2.4 V to 5 V. The reference voltage input is independent of the voltage magnitude applied to the AVDD pin. Reference Ground. Ground connection for the reference voltage. The input reference voltage (VREF+) should be decoupled to this pin. Positive Input of the Differential Analog Input. Negative Input of the Differential Analog Input. Power Supply Ground for Analog Circuitry. Synchronization and Power-Down Input Pin. This pin has dual functionality. It can be used to synchronize multiple AD7767 devices and/or put the AD7767 device into power-down mode. See the Power-Down, Reset, and Synchronization section for further details. Digital Power Supply Input. This pin can be connected directly to VDRIVE. Logic Power Supply Input, +1.8 V to +3.6 V. The voltage supplied at this pin determines the operating voltage of the digital logic interface. Serial Data Output (SDO). The conversion result from the AD7767 is output on the SDO pin as a 24-bit, twos complement, MSB first, serial data stream. Digital Logic Power Supply Ground. Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data result is available in the output register of the AD7767. See the AD7767 Interface section for further details. Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the AD7767 device. See the AD7767 Interface section for further details. Master Clock Input. The AD7767 sampling frequency is equal to the MCLK frequency. Serial Data Input. This is the daisy chain input of the AD7767. See the Daisy Chaining section for further details. Chip Select Input. The CS input selects the AD7767 device and acts as an enable on the SDO pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on the CS falling edge. The CS input allows multiple AD7767 devices to share the same SDO line. This allows the user to select the appropriate device by supplying it with a logic low CS signal, which enables the SDO pin of the device concerned. See the AD7767 Interface section for further details.
3 4 5 6 7
REFGND VIN+ VIN- AGND SYNC/PD
8 9 10 11 12 13 14 15 16
DVDD VDRIVE SDO DGND DRDY SCLK MCLK SDI CS
Rev. 0 | Page 9 of 24
AD7767 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 2.5 V 5%, VDRIVE = 1.8 V to 3.6 V, VREF = 5 V, MCLK = 1 MHz, common-mode input = VREF/2. TA = 25C, unless otherwise noted. All FFTs were generated using 8192 samples using a 4-term Blackman-Harris window.
0 -20 -40 0 -20 -40
AMPLITUDE (dB)
-80 -100 -120 -140 -160
06859-101
AMPLITUDE (dB)
-60
-60 -80 -100 -120 -140 -160
06859-104 06859-106 06859-105
-180 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz)
-180 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz)
Figure 7. AD7767 FFT, 1 kHz, -0.5 dB Input Tone
Figure 10. AD7767 FFT, 1 kHz, -6 dB Input Tone
0 -20 -40
0 -20 -40
AMPLITUDE (dB)
-60 -80 -100 -120 -140 -160
06859-102
AMPLITUDE (dB)
-60 -80 -100 -120 -140 -160 -180
-180 0 4k 8k 12k 16k 20k 24k 28k 32k FREQUENCY (Hz)
0
4k
8k
12k
16k
20k
24k
28k
32k
FREQUENCY (Hz)
Figure 8. AD7767-1 FFT, 1 kHz, -0.5 dB Input Tone
0 -20 -40 0 -20 -40
Figure 11. AD7767-1 FFT, 1 kHz, -6 dB Input Tone
AMPLITUDE (dB)
-80 -100 -120 -140 -160
06859-103
AMPLITUDE (dB)
0 4k 8k FREQUENCY (Hz) 12k 16k
-60
-60 -80 -100 -120 -140 -160 -180 0 4k 8k FREQUENCY (Hz) 12k 16k
-180
Figure 9. AD7767-2 FFT, 1 kHz, -0.5 dB Input Tone
Figure 12. AD7767-2 FFT, 1 kHz, -6 dB Input Tone
Rev. 0 | Page 10 of 24
AD7767
0 -20 -40 0 -20 -40 TONE A: 49.7kHz TONE B: 50.3kHz SECOND-ORDER IMD = -133.71dB THIRD-ORDER IMD = -109.05dB
AMPLITUDE (dB)
-80 -100 -120 -140 -160
06859-107
AMPLITUDE (dB)
-60
-60 -80 -100 -120 -140 -160
06859-110 06859-112 06859-111
-180 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz)
-180 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz)
Figure 13. AD7767 FFT, 1 kHz, -60 dB Input Tone
Figure 16. AD7767 IMD FFT, 50 kHz Center Frequency
0 -20 -40
0 -20 -40
TONE A: 24.7kHz TONE B: 25.3kHz SECOND-ORDER IMD = -133.33dB THIRD-ORDER IMD = -108.15dB
AMPLITUDE (dB)
-80 -100 -120 -140 -160
06859-108
AMPLITUDE (dB)
0 4k 8k 12k 16k 20k 24k 28k 32k
-60
-60 -80 -100 -120 -140 -160 -180 0 4k 8k 12k 16k 20k 24k 28k 32k FREQUENCY (Hz)
-180 FREQUENCY (Hz)
Figure 14. AD7767-1 FFT, 1 kHz, -60 dB Input Tone
Figure 17. AD7767-1 IMD FFT, 25 kHz Center Frequency
0 -20 -40
TONE A: 11.7kHz TONE B: 12.3kHz -20 SECOND-ORDER IMD = -137.96dB THIRD-ORDER IMD = -108.1dB -40
0
AMPLITUDE (dB)
-80 -100 -120 -140 -160
06859-109
AMPLITUDE (dB)
0 4k 8k FREQUENCY (Hz) 12k 16k
-60
-60 -80 -100 -120 -140 -160 -180 0 4k 8k FREQUENCY (Hz) 12k 16k
-180
Figure 15. AD7767-2 FFT, 1 kHz, -60 dB Input Tone
Figure 18. AD7767-2 IMD FFT, 12 kHz Center Frequency
Rev. 0 | Page 11 of 24
AD7767
-110 -112 -114 -116 AD7767-2 -120 -122 -124 -126 -128
06859-113
120
115 DYNAMIC RANGE 110
CMRR (dB)
THD (dB)
-118
105 OPEN INPUTS 100
AD7767-1
AD7767
95 FULL-SCALE 921Hz 90 0 10k 20k 30k 40k 50k 60k
-130 0 100k 200k 300k 400k 500k 600k 700k 800k 900k FREQUENCY (Hz) 1M
fNOISE (Hz)
Figure 19. AD7767/AD7767-1/AD7767-2 THD vs. MCLK Frequency
Figure 22. AD7767 CMRR vs. Common-Mode Ripple Frequency
115 114 113
200 180
AD7767-2
MAX = 8388637 MIN = 8388493 SPREAD = 145
160 140
OCCURRENCE
112
SNR (dB)
120 100 80 60
111 110 109
AD7767-1
AD7767 108 107 0 100k 200k 300k 400k 500k 600k 700k 800k 900k FREQUENCY (Hz) 1M
40 20
06859-114
0
8388493 8388497 8388501 8388505 8388509 8388513 8388517 8388521 8388525 8388529 8388533 8388537 8388541 8388545 8388549 8388553 8388557 8388561 8388565 8388569 8388573 8388577 8388581 8388585 8388589 8388593 8388597 8388601 8388605 8388609 8388613 8388617 8388621 8388625 8388629 8388633 8388637
06859-118
06859-119
CODES
Figure 20. AD7767/AD7767-1/AD7767-2 SNR and THD vs. MCLK Frequency
Figure 23. AD7767 24-Bit Histogram
150 DVDD 140
AVDD
250
MAX = 8388507 MIN = 8388608 SPREAD = 102 CODES
200
PSRR (dB)
130 VDRIVE 120
OCCURRENCE
150
100
110
50
fNOISE (Hz)
Figure 21. AD7767 Power Supply Sensitivity vs. Supply Ripple Frequency with Decoupling Capacitors
Rev. 0 | Page 12 of 24
8388508 8388512 8388516 8388520 8388524 8388528 8388532 8388536 8388540 8388544 8388548 8388552 8388556 8388560 8388564 8388568 8388572 8388576 8388580 8388584 8388588 8388592 8388596 8388600 8388604 8388608
0
10k
20k
30k
40k
50k
60k
06859-117
100
0
CODES
Figure 24. AD7767-1 24-Bit Histogram
06859-116
AD7767
350 300 250 200 150 100 50 0
8388526 8388529 8388532 8388535 8388538 8388541 8388544 8388547 8388550 8388553 8388556 8388559 8388562 8388565 8388568 8388571 8388574 8388577 8388580 8388583 8388586 8388589 8388592
06859-120
MAX = 8388593 MIN = 8388526 SPREAD = 69 CODES
3.80 3.04 2.28 1.52 LOW TEMPERATURE NOMINAL TEMPERATURE HIGH TEMPERATURE
OCCURRENCE
INL (ppm)
0.76 0 -0.76 -1.52 -2.28 -3.04 -3.80
06859-122
0
CODES
4194304 8388608 12582912 16777216 2097152 6291456 10485760 14680064 24-BIT CODES
Figure 25. AD7767-2 24-Bit Histogram
Figure 27. AD7767/AD7767-1/AD7767-2, 24-Bit INL
1.0 0.8 0.6 0.4
DNL (LSBs)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
06859-121
0
4194304 8388608 12582912 16777216 2097152 6291456 10485760 14680064 24-BIT CODES
Figure 26. AD7767/AD7767-1/AD7767-2, 24-Bit DNL
Rev. 0 | Page 13 of 24
AD7767 TERMINOLOGY
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7767, it is defined as
THD (dB ) = 20 log V 22 + V32 + V 42 + V52 + V62 V1
sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Zero Error Zero error is the difference between the ideal midscale input voltage (when both inputs are shorted together) and the actual voltage producing the midscale output code. Zero Error Drift Zero error drift is the change in the actual zero error value due to a temperature change of 1C. It is expressed as a percentage of full scale at room temperature. Gain Error The first transition (from 100...000 to 100...001) should occur for an analog voltage 1/2 LSB above the nominal negative full scale. The last transition (from 011...110 to 011...111) should occur for an analog voltage 11/2 LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. Gain Error Drift Gain error drift is the change in the actual gain error value due to a temperature change of 1C. It is expressed as a percentage of full scale at room temperature. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency f to the power of a 100 mV sine wave applied to the common-mode voltage of the VIN+ and VIN- inputs at frequency fs. CMRR (dB) = 10 log(Pf/Pfs) where Pf is the power at the frequency f in the ADC output and Pfs is the power at the frequency fs in the ADC output.
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Nonharmonic Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for the dynamic range is expressed in decibels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa - fb), and the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The AD7767 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms
Rev. 0 | Page 14 of 24
AD7767 THEORY OF OPERATION
The AD7767/AD7767-1/AD7767-2 operate using a fully differential analog input applied to a successive approximation (SAR) core. The output of the oversampled SAR is filtered using a linear phase digital FIR filter. The fully filtered data is output in a serial format, with the MSB being clocked out first. The digital filtering that follows the converter output acts to remove the out-of-band quantization noise (see Figure 30). This also has the effect of reducing the data rate from fMCLK at the input of the filter to fMCLK/8, fMCLK/16, or fMCLK/32 at the digital output, depending on which model of the device is being used. The digital filter consists of three separate filter blocks. Figure 31 shows the three constituent blocks of the filter. The order of decimation of the first filter block is set as 2, 4, or 8. The remaining sections both operate in decimate by 2.
DIGITAL FILTER STAGE 1 DATA STREAM SINC FILTER DEC x (2 x n) STAGE 2 FIR FILTER DEC x 2 STAGE 3 FIR FILTER DEC x 2 SDO
06859-019
AD7767/AD7767-1/AD7767-2 TRANSFER FUNCTION
The conversion results of the AD7767/AD7767-1/AD7767-2 are output in a twos complement, 24-bit serial format. The fully differential inputs VIN+ and VIN- are scaled by the AD7767/ AD7767-1/AD7767-2 relative to the reference voltage input (VREF+), as shown in Figure 28.
24 BITS TWOS COMPLEMENT 011...111 011...110
Figure 31. FIR Filter Stages (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2)
24-BIT OUTPUT
000...010 000...001 000...000 111...111 111...110
100...001 100...000 VIN+ = 0V VIN- = VREF - 1LSB VREF VIN+ = 2 VREF VIN- = 2 VIN+ = VREF - 1LSB VIN- = 0V
06859-012
Table 6 shows the three available models of the AD7767, listing the change in output data rate relative to the order of decimation rate implemented. This brings into focus the trade-off that exists between extra filtering and reduction in bandwidth, whereby using a filter option with a larger decimation rate increases the noise performance while decreasing the usable input bandwidth. Table 6. AD7767 Models
Model AD7767 AD7767-1 AD7767-2 Decimation Rate 8 16 32 Output Data Rate (ODR) 128 kHz 64 kHz 32 kHz
Figure 28. AD7767/AD7767-1/AD7767-2 Transfer Function
CONVERTER OPERATION
Internally, the input waveform applied to the SAR core is converted and an equivalent digital word is output to the digital filter at a rate equal to MCLK. By employing oversampling, the quantization noise of the converter is spread across a wide bandwidth from 0 to fMCLK. This means that the noise energy contained in the signal band of interest is reduced (see Figure 29).
Note that the output data rates shown in Table 6 are realized when using the maximum MCLK input frequency of 1.024 MHz. The output data rate scales linearly with the MCLK frequency, as does the digital power dissipated in the device. The settling time of the filter implemented on the AD7767, AD7767-1, and AD7767-2 is related to the length of the filter employed. The response of the filter in the time domain sets the filter settling time. Table 7 shows the filter settling times of the AD7767/AD7767-1/AD7767-2. The frequency responses of the digital filters on the AD7767, AD7767-1, and AD7767-2 are shown in Figure 32, Figure 33, and Figure 34, respectively. At the Nyquist frequency (output data rate/2), the digital filter provides 6 dB of attenuation. In each case, the filter provides stop-band attenuation of 100 dB and pass-band ripple of 0.005 dB.
QUANTIZATION NOISE BAND OF INTEREST
fMCLK/2
Figure 29. Quantization Noise
DIGITAL FILTER CUTOFF FREQUENCY
BAND OF INTEREST
fMCLK/2
Figure 30. Digital Filter Cutoff Frequency
Rev. 0 | Page 15 of 24
06859-214
06859-213
AD7767
0 -20 -40
ANALOG INPUT STRUCTURE
The AD7767/AD7767-1/AD7767-2 are configured as a differential input structure. A true differential signal is sampled between the analog inputs VIN+ and VIN-, Pin 4 and Pin 5, respectively. Using differential inputs provides rejection of signals that are common to both the VIN+ and VIN- pins. Figure 35 shows the equivalent analog input circuit of the AD7767/AD7767-1/AD7767-2. The two diodes on each of the differential inputs provide ESD protection for the analog inputs.
VREF+ D VIN+ C1 GND D AGND VREF+ RIN C2
AMPLITUDE (dB)
-60 -80 -100 -120 -140 -160 0 16k 32k 48k 64k 80k 96k 112k 128k FREQUENCY (Hz)
Figure 32. AD7767 Digital Filter Frequency Response
0
06859-216
D
-20 -40
VIN- C1 D AGND
RIN
C2
AMPLITUDE (dB)
GND
-60 -80 -100 -120 -140 -160 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz)
Figure 35. Equivalent Analog Input Structure
Take care to ensure that the analog input signal does not exceed the reference supply voltage VREF+ by more than 0.3 V as specified in the Absolute Maximum Ratings section. The diodes become forward biased if the input voltage exceeds this limit and start to conduct current. The diodes can handle 130 mA maximum. The impedance of the analog inputs can be modeled as a parallel combination of C1 and the network formed by the series connection of RIN, C1, and C2. The value of C1 is dominated by the pin capacitance. RIN is typically 1.4 k, the lumped component of serial resistors and the RON of the switches. C2 is typically 22 pF, and its value is dominated by the sampling capacitor.
06859-217
Figure 33. AD7767-1 Digital Filter Frequency Response
0 -20 -40
SUPPLY AND REFERENCE VOLTAGES
The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply applied to the DVDD, AVDD pins. The interface is specified to operate between 1.7 V and 3.6 V. The AD7767/AD7767-1/ AD7767-2 operate from a 5 V reference applied to the VREF+ pin. The recommended reference devices are the ADR445 or the ADR425. The 5 V reference operates both as a reference supply and as a power supply to the AD7767/AD7767-1/AD7767-2 device. This feature means that the full-scale differential input range of the AD7767/AD7767-1/AD7767-2 is 10 V. See the Driving the AD7767 section for details on the maximum input voltage.
AMPLITUDE (dB)
-60 -80 -100 -120 -140 -160 0 4k 8k 12k 16k 20k 24k 28k 32k FREQUENCY (Hz)
Figure 34. AD7767-2 Digital Filter Frequency Response
Rev. 0 | Page 16 of 24
06859-218
06859-219
AD7767 AD7767 INTERFACE
The AD7767 provides the user with a flexible serial interface, enabling the user to implement the most desirable interfacing scheme for their application. The AD7767 interface comprises seven different signals. Five of these signals are inputs: MCLK, CS, SYNC/PD, SCLK, and SDI. There are two output signals: DRDY and SDO. devices indicating permission to use the bus. When CS is logic high, the SDO line of the AD7767 is tristated. There are two distinct patterns that can be initiated to read data from the AD7767 device; these are for the cases when the CS falling edge occurs after the DRDY falling edge and for the case when the CS falling edge occurs before the DRDY falling edge (when CS is set to logic low). When the CS falling edge occurs after DRDY falling edge, the MSB of the conversion result is available on the SDO line on this CS falling edge. The remaining bits of the conversion result (MSB-1, MSB-2, and so on) are clocked onto the SDO line by the falling edges of SCLK that follow the CS falling edge. Figure 3 details this interfacing scheme. When CS is tied low, the AD7767 serial interface can operate in 3-wire mode as shown in Figure 4. In this case, the MSB of the conversion result is available on the SDO line on the falling edge of DRDY. The remaining bits of the data conversion result (MSB-1, MSB-2, and so on) are clocked onto the SDO line by the subsequent SCLK falling edges.
INITIAL POWER-UP
On initial power-up, apply a continuous MCLK signal. It is recommended that the user reset the AD7767 to clear the filters and ensure correct operation. The reset is completed as described in Figure 5, with all events occurring relative to the rising edge of MCLK. A negative pulse on the SYNC/PD input initiates the reset, and the DRDY output switches to logic high and remains high until valid data is available. Following the power-up of the AD7767 by transitioning the SYNC/PD pin to logic high, a settling time is required before valid data is output by the device. This settling time, tSETTLING, is a function of the MCLK frequency and the decimation rate. Table 7 lists the settling time of each of the AD7767 models and should be referenced to Figure 5. Table 7. Filter Settling Time After SYNC/PD
Model AD7767 AD7767-1 AD7767-2
1
POWER-DOWN, RESET, AND SYNCHRONIZATION
The AD7767 SYNC/PD pin allows the user to synchronize multiple AD7767 devices. This pin also allows the user to reset and power down the AD7767 device. These features are implemented relative to the rising edges of MCLK and are shown in Figure 5. To power down, reset, or synchronize a device, the AD7767 SYNC/PD pin should be taken low. On the first rising edge of MCLK, the AD7767 is powered down. The DRDY pin transitions to logic high, indicating that the data in the output register is no longer valid. The status of the SYNC/PD pin is checked on each subsequent rising edge of MCLK. On the first rising edge of MCLK after the SYNC/PD pin is taken high, the AD7767 is taken out of power-down. On the next rising edge, the filter of the AD7767 is reset. On the following rising edge, the first new sample is taken. A settling time, tSETTLING, from the filter reset, must pass before valid data is output by the device (as listed in Table 7). The DRDY output goes logic low after tSETTLING to indicate when valid data is available on SDO for readback.
Decimation Rate 8 16 32
tSETTLING 594 x (tMCLK + t21) 1186 x (tMCLK + t21) 2370 x (tMCLK + t21)
1
tSETTLING is measured from the first MCLK rising edge after the rising edge of SYNC/PD to the falling edge of DRDY.
READING DATA
The AD7767 outputs its data conversion results in an MSB first, twos complement, 24-bit format on the serial data output pin (SDO). MCLK is the master clock, which controls all the AD7767 conversions. The SCLK is the serial clock input for the device. All data transfers take place with respect to the SCLK signal. The DRDY line is used as a status signal to indicate when the data is available to be read from the AD7767. The falling edge of DRDY indicates that a new data-word is available in the output register of the device. DRDY stays low during the period that output data is permitted to be read from the SDO pin. The DRDY signal returns to logic high to indicate when not to read from the device. Ensure that a data read is not attempted during this period as the output register is being updated. The AD7767 offers the user the option of using a chip select input signal (CS) in its data read cycle. The CS signal is a gate for the SDO pin and allows many AD7767 devices to share the same serial bus, acting as an instruction signal to each of these
Rev. 0 | Page 17 of 24
AD7767 DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same digital interface lines by cascading the outputs of multiple ADCs on a single data line. This feature is especially useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register where data is clocked on the falling edge of SCLK. The block diagram in Figure 36 shows the way in which devices must be connected in order to achieve daisy chain functionality. This scheme operates by passing the output data of the SDO pin of an AD7767 device to the SDI input of the next AD7767 device in the chain. The data then continues through the chain until it is clocked onto the SDO pin of the first device on the chain. device in the chain while its DRDY signal is active low. This is illustrated in the example shown where the conversion results from devices A, B, C, and D are clocked onto SDO (A) in the time between the falling edge of DRDY (A) and the rising edge of DRDY (A).
CHOOSING THE SCLK FREQUENCY
As shown in Figure 36, the number of SCLK falling edges that occur during the period when DRDY (A) is active low must match the number of devices in the chain multiplied by 24 (the number of bits that must be clocked through onto SDO (A) for each device). The period of SCLK (tSCLK) required for a known daisy chain length using a known common MCLK frequency must therefore be established in advance. Note that the maximum SCLK frequency is governed by t8 and is specified in the Timing Specifications table for different VDRIVE voltages. In the case where CS is tied logic low,
t t SCLK READ 24 x K
READING DATA IN DAISY CHAIN MODE
An example of a daisy chain of four AD7767 devices is shown in Figure 36 and Figure 37. In the case illustrated in Figure 36, the output of AD7767 (A) is the output of the full daisy chain. The last device in the chain (AD7767 (D)) has its serial data in (SDI) pin connected to ground. All the devices in the chain must use common MCLK, SCLK, CS, and SYNC/PD signals. To enable the daisy chain conversion process, apply a common SYNC/PD pulse to all devices, synchronizing all the devices in the chain (see the Power-Down, Reset, and Synchronization section). After applying a SYNC/PD pulse to all the devices, there is a delay (as listed in Table 7) before valid conversion data appears at the output of the chain of devices. As shown in Figure 37, the first conversion result is output from the device labeled AD7767 (A). This 24-bit conversion result is followed by the conversion results from the devices B, C, and D, respectively, with all conversion results output in an MSB first sequence. The stream of conversion results is clocked through each device in the chain and is eventually clocked onto the SDO pin of the AD7767 (A) device. The conversion results of the all the devices in the chain must be clocked onto the SDO pin of the final
(1)
where: K is the number of AD7767 devices in the chain. tSCLK is the period of the SCLK. tREAD equals t DRDY - t5. In the case where CS is used in the daisy chain interface,
) - (t 6 + t 7 + t 13 ) (t t SCLK READ 24 x K
where: K is the number of AD7767 devices in the chain.
(2)
Note that the maximum value of SCLK is governed by t8 and is specified in the Timing Specifications table for different VDRIVE voltages.
Rev. 0 | Page 18 of 24
AD7767
DAISY CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS
SYNC/PD CS
SYNC/PD CS CS
SYNC/PD CS
SYNC/PD CS
SYNC/PD DRDY
AD7767
SDI SDI SCLK MCLK SCLK MCLK
AD7767
SDI SCLK MCLK
AD7767
SDI SCLK MCLK
AD7767
SDI SCLK MCLK
06859-013
(D) SDO
(C) SDO
(B) SDO
(A) SDO
Figure 36. AD7767 Daisy Chain Configuration with Four AD7767 Devices
MCLK
1
8xn
DRDY (A)
CS 24 x tSCLK SCLK AD7767 (A) AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (C) AD7767 (D) AD7767 (D) AD7767 (A) AD7767 (B) AD7767 (C) AD7767 (D)
06859-014 06859-015
24 x tSCLK
24 x tSCLK
24 x tSCLK
SDO (A) SDI (A) = SDO (B) SDI (B) = SDO (C) SDI (C) = SDO (D)
Figure 37. AD7767 Daisy Chain Timing Diagram (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) Driving the AD7767
MCLK
1
DRDY (A)
CS
SDO (A)
MSB (A)
LSB (A) MSB (B)
LSB (B) MSB (C)
LSB (C)
SCLK
t16
SDI (A) = SDO (B) MSB (B)
t17
LSB (B) MSB (C) LSB (C) MSB (D) LSB (D)
Figure 38. AD7767 Daisy Chain SDI Setup and Hold Timing
Rev. 0 | Page 19 of 24
AD7767 DRIVING THE AD7767
The AD7767 must be driven with fully differential inputs. The common-mode voltage of the differential inputs to the AD7767 device and thus the limits on the differential inputs are set by the reference voltage VREF applied to the device. The commonmode voltage of the AD7767 is VREF/2. Where the AD7767 VREF+ pin is supplied with a 5 V supply (the ADR445 or ADR425), the common mode is at 2.5 V. This means that the maximum inputs that can be applied on the AD7767 differential inputs are a 5 V p-p input around 2.5 V.
VREF
DIFFERENTIAL SIGNAL SOURCE
An example of some recommended driving circuitry that can be employed in conjunction with the AD7767/AD7767-1/ AD7767-2 is shown in Figure 40. Figure 40 shows how the ADA4841-1 device can be used to drive an input to the AD7767/ AD7767-1/AD7767-2 from a differential source. Each of the differential paths is driven by an ADA4841-1 device.
499 3.3nF AIN+ 499 ADA4841-1 3.3
1
2.5V
VREF 2
VIN+
499
0V
4
VIN+ VIN-
AVDD VREF+
2
10nF 3.3nF
5
AD7767
VREF
AIN-
VIN- VREF 2
06859-016
499 ADA4841-1 2x VCM 1k 3.3
ADR425
0V
Figure 39. Maximum Differential Inputs to the AD7767
Figure 40. Driving the AD7767 from a Fully Differential Source
An analog voltage of 2.5 V supplies the AD7767 AVDD pin. However, the AD7767 allows the user to apply a reference voltage of up to 5 V. This provides the user with an increased full-scale range, offering the user the option of using the AD7767 with a larger LSB voltage size. Figure 39 shows the maximum and minimum inputs to the AD7767.
SINGLE-ENDED SIGNAL SOURCE
In the case where the AD7767 is being supplied from a singleended source, the application circuit in Figure 41 can be used to drive the AD7767 device. Figure 41 shows how the ADA4941-1 single-to-differential amplifier can be used to create a fully differential input to the AD7767. The single-ended signal input is applied to the positive input of the ADA4941-1 device. Arrange the values of the resistor elements to create a 2.5 V common-mode input to the AD7767/AD7767-1/AD7767-2 device. R3 and C2 default to 3.3 and 10 nF, respectively.
VSS-
AIN+
R1 R1 C1
8 7
2.5V
6 5
OUT-
IN
DIS
V-
R3 C2
1 4 VIN+ 5 VIN-
AVDD VREF+
2
AD7767
ADA4941-1
OUT+ REF FB V+
R3
1
2
3
4
ADR425
VOFFSET
R4 C3 R5
R2 VSS+ 2x VCM R2 RFB CFB
06859 -018
Figure 41. Driving the AD7767 from a Single-Ended Source
Rev. 0 | Page 20 of 24
06859-017
1k
AD7767
ANTIALIASING
The AD7767/AD7767-1/AD7767-2 sample the analog input at a maximum rate of 1.024 MHz. The on-board digital filter provides up to 100 dB attenuation of any possible aliasing frequencies in the range from the beginning of the filter stop band (0.547 x ODR) to where the image of the digital filter pass band occurs at MCLK - filter stop band (MCLK - 0.547 x ODR), which is the first alias point. This is illustrated in Figure 42.
fMCLK
in use. For instance, operating the AD7767 device with an MCLK of 800 kHz gives an output data rate of 100 kHz due to the decimate by 8 filtering.
4.5 4.0 3.5 DIDD
CURRENT (mA)
3.0 2.5 2.0 1.5 1.0 0.5 0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k FREQUENCY (Hz) AIDD
DIGITAL FILTER 100dB ANTIALIAS PROTECTION
DIGITAL FILTER IMAGE AT fMCLK
06859-231
IREF
06859-226
BAND OF INTEREST
fMCLK - (0.547 x ODR)
FIRST ALIAS POINT
Figure 42. AD7767/AD7767-1/AD7767 Spectrum
Table 8 shows the attenuation achieved by various orders of front-end antialias filters prior to the AD7767/AD7767-1/ AD7767-2 at the image of the digital filter stop band, which is 1.024 MHz - 0.547 x ODR. Table 8. Antialias Filter Order Attenuation at First Alias Point
CURRENT (mA)
Figure 43. AD7767 Current vs. MCLK Frequency
2.5
2.0 DIDD 1.5
Model AD7767
AD7767-1
AD7767-2
Filter Order 1st 2nd 3rd 1st 2nd 3rd 1st 2nd 3rd
Attenuation at 1.024 MHz - 0.547 x ODR 27 dB 50 dB 70 dB 33 dB 62 dB 89 dB 38 dB 74 dB 110 dB
1.0 AIDD 0.5 IREF 0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k FREQUENCY (Hz)
Figure 44. AD7767-1 Current vs. MCLK Frequency
The AD7764 and AD7765 sigma-delta devices are available to customers that require extra antialias protection. These devices sample internally at a rate of 20 MHz to achieve up to a maximum of 156 kHz or 312 kHz output data rate. This means that the first alias point of these devices when run at the maximum speeds are 19.921 MHz and 19.843 MHz, respectively.
CURRENT (mA)
1.4 DIDD 1.2 1.0 AIDD 0.8 0.6 0.4 0.2 0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k FREQUENCY (Hz)
POWER DISSIPATION
The AD7767/AD7767-1/AD7767-2 offer exceptional performance at ultralow power. Figure 43, Figure 44, and Figure 45 show how the current consumption of the AD7767/AD7767-1/ AD7767-2 scales with the MCLK frequency applied to the device. Both the digital and analog currents scale as the MCLK frequency is reduced. The actual throughput of each of the AD7767/AD7767-1/AD7767-2 equals the MCLK frequency applied divided by the decimation rate employed by the device
IREF
Figure 45. AD7767-2 Current vs. MCLK Frequency
Rev. 0 | Page 21 of 24
06859-228
06859-227
AD7767
VREF+ INPUT SIGNAL
The AD7767/AD7767-1/AD7767-2 VREF + pin is supplied with a 5 V input, which is generated by a low noise voltage reference. Either the ADR445 or the ADR425 can be used with the AD7767/ AD7767-1/AD7767-2 device. This reference voltage input also acts as a power supply to the AD7767/AD7767-1/AD7767-2 device. The output of the low noise voltage reference does not require a buffer; however, it is important to provide a passive filter network between the VOUT pin of the voltage reference and the VREF+ input on the ADC. Figure 46 shows a reference signal network that can be used with both the ADR445 and the ADR425. The 100 nF capacitor on the output of the ADR445 or ADR425 stabilizes the reference output voltage. The series resistor coupled with the other capacitive values on the reference acts as a lowpass filter. Figure 46 shows the optimal reference voltage input circuit.
VOUT 5V 100 C40 100F C15 10F VREF+ C38 100nF
MULTIPLEXING ANALOG INPUT CHANNELS
The AD7767/AD7767-1/AD7767-2 can be used with a multiplexer configuration. As per any converter that uses a digital filtering block, the maximum switching rate, or output data rate per channel, is a function of the digital filter settling time. A user multiplexing the analog inputs to a converter that employs a digital filter must wait the full digital filter settling time before a valid conversion result is achieved; at this point, the channel can be switched. After switching the channel, the full settling time must again be observed before a valid conversion result is available and the input is switched once more. The AD7767 filter settling time equals 74 divided by the output data rate in use. The maximum switching frequency in a multiplexed application is therefore 1/(74/ODR), where the output data rate (ODR) is a function of the applied MCLK frequency and the decimation rate employed by the device in question. For example, applying a 1.024 MHz MCLK frequency to the AD7767 gives a maximum output data rate of 128 kHz, which in turn allows a 1.729 kHz multiplexer switching rate. The AD7767-1 and the AD7767-2 employ digital filters with longer settling time to achieve greater precision; thus, the maximum switching frequency for these devices is 864 Hz and 432 Hz, respectively.
Figure 46. AD7767/AD7767-1/AD7767-2 Reference Filtering, ADR445 or ADR425 Circuit Topology
For the capacitor designated C40 in Figure 46, either an electrolytic or tantalum capacitor can be used. This capacitor acts as a reservoir of charge. Further decoupling capacitors are placed as close as possible to the VREF+ pin.
06859-229
ADR445 OR ADR425
C39 100nF
AD7767/ AD7767-1/ AD7767-2
Rev. 0 | Page 22 of 24
AD7767 OUTLINE DIMENSIONS
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7767BRUZ 1 AD7767BRUZ-RL71 AD7767BRUZ-11 AD7767BRUZ-1-RL71 AD7767BRUZ-21 AD7767BRUZ-2-RL71 EVAL-AD7767EDZ1 EVAL-AD7767-1EDZ1 EVAL-AD7767-2EDZ1 EVAL-CED1Z1
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Evaluation Board Evaluation Board Converter Evaluation and Development Board
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
AD7767 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06859-0-8/07(0)
Rev. 0 | Page 24 of 24

▲Up To Search▲

Price & Availability of AD7767

	To Download AD7767 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .